EECS665

For this trial, you should enhance the intermediate code generation module such that it outputs LLVM bitcode when the -l option is given. The output of your IR codegen phase should be parseable by the llvm-as assembler, and should be runnable after the output of llvm-as goes through llvm-ld.

You may enhance your existing levic source code to complete this trial.

Submit a complete source code tarball, including a makefile.